Multi-chip packaging is an advanced high-density packaging technology to vertically stacking a plurality of dice within the same package. The existing packaging method is to stack individual chips onto a substrate followed by corresponding packaging and testing processes. However, using a substrate increases overall package thickness and footprint.
In order to reduce the dimension of a multi-chip package, there is an attempt to stack a plurality of chips using wafer-to-wafer bonding to manufacture a substrate-less chip cube such as related technology revealed in US Patent No. 2011/0074017. However, bad chips are always randomly present within a wafer, therefore, wafer-to-wafer bonding would cause overall packaging yield of substrate-less chip cubes to drop. Moreover, when a substrate is eliminated, the pitch between the external electrical electrodes or/and the testing electrodes of a chip cube is shrunk from a few hundred micrometer down below a hundred micrometer so that the existing pogo pins of a tester for conventional semiconductor packages can not be used. There are two solutions to resolve the shrunk pitch issue. The first one is to directly SMT bond the substrate-less chip cube onto a board without any testing followed by a module test without ensuring the electrical joints between the stacked chips good or bad. The other one is to directly mount the substrate-less chip cube onto an interposer (normally made of Si) with fan-out circuitry and fan-out electrodes then load the interposer into a tester having pogo pins to perform testing where the overall testing cost is quite complicated and expensive.